1. Field of the Invention
The present invention relates to a control gate, such as a floating gate in a memory device, and a method of making the same, but more particularly to a self-aligned shallow trench isolation technique that simultaneously forms a gate and an active region thereof.
2. Description of the Related Art
During the manufacture of memory devices, the packing density of cells is primarily determined by the layout of cells within the array and the physical dimensions of the cells themselves. Below the half-micron design rule, scalability is limited by photolithographic resolution attainable during manufacturing and by alignment tolerances of masks used during production. Alignment tolerances are, in turn, limited by mechanical techniques employed to form masks and the techniques used to register these masks between layers. Because alignment errors accumulate during multi-stage fabrication, it is preferable to use as few masks as possible. Fewer masks minimizes the likelihood of misalignment. Accordingly, xe2x80x9cself-alignmentxe2x80x9d processing steps have been developed to produce semiconductor devices.
Isolation structures, e.g., field oxides, between individual cells within the memory cell array consume regions of the chip that are otherwise useful for active circuitry. Thus, in order to increase the packing density of memory cells and active circuits within the substrate, it is desirable to minimize the size of these isolation structures. However, the size of the isolation structure is generally dictated by their process of formation and/or the alignment of this structure.
Typically, an isolation structure is grown at various regions of the chip by a thermal field oxidation process, such as a LOCal Oxidation of Silicon (hereinafter referred to as xe2x80x9cLOCOSxe2x80x9d). According to the LOCOS method, after a pad oxide layer and a nitride layer are successively formed, the nitride layer is subjected to patterning. Then, the patterned nitride layer is used as a mask to selectively oxidize the silicon substrate to form field oxide regions. However, in considering the LOCOS isolation, the growth of oxide may encroach upon the side plane of the pad oxide layer at a lower portion of the nitride layer serving as the mask during selective oxidation of the silicon substrate, thereby creating what is called a bird""s beak at the end portion of the field oxide layer. Due to the bird""s beak, the field oxide layer extends into the active region of the memory cell thereby decreasing the width of the active region. This phenomenon is undesirable because it degrades the electrical characteristics of the memory device.
For this reason, a shallow trench isolation (hereinafter referred to as xe2x80x9cSTIxe2x80x9d) structure is attractive in making ultra-high scale semiconductor devices. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide layer is deposited to fill up the trench. Thereafter, the oxide layer is etched via an etch back or a chemical mechanical planarizing (CMP) method so as to form a field oxide layer inside the trench.
The foregoing LOCOS and STI methods commonly include a mask step that defines the regions on the substrate of the isolation structure and a step that forms the field oxide layer within those regions. After forming the isolation structure, steps to form the memory cells are carried out. As such, alignment errors associated with forming the isolation structure and memory cells aggregate to induce mis-alignment, which may result in failure of the device.
When making a floating gate of a non-volatile memory device, for example, one method of reducing misalignment includes forming LOCOS isolation structure using a self-aligned floating gate, such as by the process disclosed in U.S. Pat. No. 6,013,551 (issued to Jong Chen, et al.). According to the methods described therein, a floating gate and active region thereof are simultaneously defined and fabricated using a single mask so that alignment errors do not aggregate.
Non-volatile memory devices are used in flash memory devices and have long-time storage capacity, e.g., almost indefinitely. In recent years, demand for such electrically programmable flash memory devices, EEPROMS for example, has increased. Memory cells of these devices generally have a vertically stacked gate structure comprising a floating gate formed at an upper portion of the silicon substrate. The multi-layer gate structure typically includes one or more tunnel oxide or dielectric layers and a control gate over and/or around the floating gate. In a flash memory cell having this structure, data is stored by transferring electrons to and from the floating gate, which is achieved by applying a controlled voltage to the control gate and substrate. The dielectric functions to maintain the potential on the floating gate.
Even though self-aligned STI processes have an advantage of simultaneously forming floating gates and active regions, there is still a drawback because the aspect ratio of gaps formed in the process is increased, which is likely to form seams or voids within the trench during the gap filling. Also, when using a high density plasma (hereinafter referred to as xe2x80x9cHDPxe2x80x9d) oxide layer to fill these gaps, the edge portion of a polishing end-point detecting layer underlying the HDP oxide layer becomes eroded during deposition of the HDP oxide layer, which undesirably provides a negative slope at the field oxide region. For this reason, gate residues are generated around the bottom of the sloped portion of the field regions during subsequent gate etching procedures.
The above-described problems can be solved by optimizing the conditions during deposition of the HDP oxide layer to enhance the gap filling capability or by using a method that eliminates the negative slope at the field region by means of a wet etchant.
FIGS. 1A to 1E are perspective views of a substrate illustrating in succession a method of manufacturing a conventional flash memory device using a self-aligned STI technique.
Referring to FIG. 1A, after forming a gate oxide layer (i.e., tunnel oxide layer) 11 on a silicon substrate 10, a first polysilicon layer 13 and a nitride layer 15 are successively formed on the gate oxide layer 11.
Referring to FIG. 1B, a photolithography process is performed to pattern the nitride layer 15, the first polysilicon layer 13, and the gate oxide layer 11 to form a nitride layer pattern 16, a first floating gate 14, and a gate oxide layer pattern 12. Thereafter, exposed portions of the substrate 10 are etched to a predetermined depth to form trench 18. That is, the active regions and floating gates are simultaneously defined during the trench forming process using a single mask.
Referring to FIG. 1C, exposed portions of the trench 18 are subjected to thermal treatment in ambient oxygen atmosphere for curing the silicon damage caused by high energy ion impact during the trench etching process. By doing so, a trench oxide layer 20 is formed along the inner surface including the bottom plane and sidewall of the trench 18 by the oxidation reaction of the exposed silicon with an oxidant.
During the above oxidizing process, the oxidant encroaches upon the side of the gate oxide layer pattern 12 at the lower portion of the first floating gate 14 to form the bird""s beaks at both ends of the gate oxide layer pattern 12. Because of the bird""s beaks, the bottom edge portions of the first floating gate 14 are bent outward while both end portions of the gate oxide layer pattern 12 expand, the lower portions of the sidewalls of the first floating gate 14 have positive slope. Here, the positive slope denotes that the slope allows the sidewall erosion with respect to the etchant. In other words, as shown in the drawing, the intrusion of the oxidant into the portion underlying the nitride layer pattern 16 is blocked by the existence of the nitride layer pattern 16 to provide the negative slope at the upper portion of the sidewall of the first floating gate 14. Meanwhile, the bottom edge portion of the lower portion of the first floating gate 14 is bent outward to have a positive slope, which is eroded by etchant introduced from the upper portion of the substrate in the same manner as in the sidewall of a mesa structure or to act as a stopping layer of the underlying layer when the etchant is applied, which is undesirable.
Referring to FIG. 1D, after forming an oxide layer (not shown) via a chemical vapor deposition (hereinafter referred to as xe2x80x9cCVDxe2x80x9d) method for filling up the trench 18, the CVD-oxide layer is removed via a CMP process until the upper surface of the nitride layer 16 pattern is exposed. As the result, a field oxide layer 22 including the trench oxide layer 18 is formed inside the trench 18.
After removing the nitride layer pattern 16 via a phosphoric acid stripping process, a material identical to that of the first polysilicon layer 13 is deposited to form a second polysilicon layer (not shown) for the purpose of forming a second floating gate on the upper portion of the first floating gate 14 and the field oxide layer 22. The second polysilicon layer over the field oxide layer 22 is partially etched via a photolithography process to form a second floating gate 24 in a cell that is separated from those of neighboring cells. The second floating gate 24 electrically contacts the first floating gate 14 and functions to increase the area of the dielectric interlayer which is formed in a subsequent process.
Then, an ONO dielectric interlayer 26 and a control gate layer 28 are successively formed on the entire surface of the resultant structure. The control gate layer 28 is generally formed by a polycide structure obtained by stacking a doped polysilicon layer and a tungsten silicide layer.
In FIG. 1E, the control gate layer 28 is patterned via a photolithography process. Successively, the exposed dielectric interlayer 26 and the second and first floating gates 24 and 14 are anisotropically etched via a dry etch process to complete the non-volatile memory device.
At this time, as shown in the portion denoted by a dotted line A in FIG. 1D, the lower portion of the sidewall of the first floating gate 14 has a positive slope. Therefore, by the characteristic of the anisotropic etching (i.e., where etching is performed only in the vertical direction) of the dry etch process, the bottom edge portion of the first floating gate 14 masked by the field oxide layer 22 is not etched to remain intact. As the result, a line-shaped polysilicon residues 14a is formed along the surface boundary of the field oxide layer 22 and the active region. The polysilicon residue 14a forms an electrical bridge between adjacent floating gates, which causes an electrical fail of the device.
Therefore, it is an object of the present invention to provide a method of manufacturing a non-volatile memory or other device having a gate or other conductive structure of a desired profile, such as a floating gate structure in a flash memory device, that avoids a positive slope on sidewalls thereof during formation.
To achieve the above aspect of the invention, there is provided a self-alignment method of making and a corresponding semiconductor device that includes a floating gate and an associated active region thereof. The floating gate and active region are formed in a substrate of a semiconductor memory device in a region bounded at least, in part, by a field oxide region formed in a trench. The trench is formed together with forming at least a first segment of the floating gate. The method includes uniformly forming an oxide at sidewalls of a first segment of the floating gate by, prior to forming the trench, forming a buffer layer over a first segment of the gate and subsequently removing the buffer layer. This achieves more even oxidation of sidewalls of the first segment before layering at least another segment of conductive material over the first segment of the floating gate.
In another embodiment, a gate oxide layer is formed on a semiconductor substrate, a first conductive layer is formed on the gate oxide layer, and a buffer layer (e.g., an oxide layer) is formed on the first conductive layer. Then, a stopping layer is formed on the buffer layer, and the stopping layer and buffer layer are patterned to form a stopping layer pattern and a buffer layer pattern. Thereafter, the first conductive layer and the gate oxide layer are patterned to form a floating gate layer as a first conductive layer pattern and a gate oxide layer pattern, and the upper portion of the substrate is etched to form a trench. The inner surface portion of the trench is oxidized to form a trench oxide layer along the inner surface of the trench, and bird beaks are formed at the upper and lower portions of the floating gate layer to prevent the formation of a positive profile at the sidewall of the patterned floating gate layer. Finally, a field oxide layer is formed for filling up the trench.
Furthermore, to achieve the above features of the invention, a method of manufacturing a memory device is carried out by forming a gate oxide layer on a semiconductor substrate, forming a first conductive layer on the gate oxide layer, and forming a buffer layer, such as an oxide layer, on the first conductive layer. Then, a stopping layer is formed on the buffer layer. The stopping layer, the buffer layer, the first conductive layer, the gate oxide layer and substrate are patterned by using a single mask for forming a floating gate from the first conductive layer. Also, simultaneously, a trench aligned with the floating gate is formed within the substrate adjacent to the floating gate for defining an active region of the substrate. Thereafter, the inner surface portion of the trench is oxidized to form a trench oxide layer along the inner surface of the trench, and birds beaks are formed at the upper and lower portions of the floating gate layer to prevent the formation of a positive profile at the sidewall of the patterned floating gate layer. Finally, a field oxide layer is formed for filling up the trench.
According to another aspect of the invention, a buffer layer is formed between the floating gate layer and the nitride layer which is used as an oxidation mask layer to generate the birds beaks at both the upper and lower portions of the floating gate layer during the subsequent oxidizing of the sidewalls. By doing so, the bird""s beaks prevent the sidewalls of the floating gate layer from having the positive slope, which prevents failure of the device induced by the gate residues during following etching of the gate.
In addition to methods, the invention further includes a floating gate semiconductor memory device and components thereof as defined by the appended claims.